1. Field of the Invention
The present invention relates to level shifters and, more particularly, to a level shifter that provides high-speed operation between power domains that have a large voltage difference.
2. Description of the Related Art
A level shifter is a common circuit device that is used to translate a logic signal from a first power domain to a second power domain. A deep sub-micron digital circuit can represent a logic low with ground and a logic high with a voltage of, for example, 1.2 volts. When this circuit communicates with another circuit that represents a logic low with ground and a logic high with a voltage of, for example, 3.6 volts, a level shifter is used to shift the 1.2V logic high to a 3.6V logic high.
FIG. 1 shows a circuit diagram that illustrates a prior art level shifter 100. As shown in FIG. 1, level shifter 100 includes an inverter that has a PMOS transistor M1 and an NMOS transistor M2. PMOS transistor M1 has a source connected to a first voltage source VDD1, such as 1.2V, a gate connected to an input node IN, and a drain. NMOS transistor M2 has a drain connected to the drain of PMOS transistor M1, a source connected to ground, and a gate connected to the input node IN.
As further shown in FIG. 1, level shifter 100 also has an NMOS transistor M3 and an NMOS transistor M4. NMOS transistor M3 has a source connected to ground VSS, a drain connected to an inverted output node OUTbar, and a gate connected to the gates of transistors M1 and M2. NMOS transistor M4, which is substantially the same size as NMOS transistor M3, has a source connected to ground VSS, a drain connected to an output node OUT, and a gate connected to the drains of transistors M1 and M2.
Level shifter 100 further has a PMOS transistor M5 and a PMOS transistor M6. PMOS transistor M5 has a source connected to a second voltage source VDD2, such as 3.6V, a drain connected to the inverted output node OUTbar, and a gate connected to the output node OUT. PMOS transistor M6, which is substantially the same size as transistor M5, has a source connected to the second voltage source VDD2, a drain connected to the output node OUT, and a gate connected to the inverted output node OUTbar.
In operation, when a logic low, represented by ground, is present on the input node IN, PMOS transistor M1 is turned on and NMOS transistors M2 and M3 are turned off. When PMOS transistor M1 is turned on, the first supply voltage VDD1 is placed on the gate of NMOS transistor M4 which, in turn, turns on NMOS transistor M4. When NMOS transistor M4 is turned on, the voltage on the output node OUT is pulled down to ground. Thus, the logic state on the output node OUT of level shifter 100 matches the logic state on the input node IN.
When the voltage on the output node OUT is pulled down to ground by NMOS transistor M4, PMOS transistor M5 is turned on. When PMOS transistor M5 is turned on, the second supply voltage VDD2 is placed on the gate of PMOS transistor M6 which, in turn, turns off PMOS transistor M6.
In addition, the second supply voltage VDD2 is also placed on the inverted output node OUTbar. Thus, the logic state on the inverted output node OUTbar of level shifter 100 is the inverse of the logic state on the input node IN. Further, the voltage level of the logic high state has been level shifted up from 1.2V to 3.6V.
When the logic state on the input node IN transitions from a logic low to a logic high, PMOS transistor M1 turns off and NMOS transistors M2 and M3 turn on. When NMOS transistor M2 turns on, NMOS transistor M2 pulls down the voltage on the gate of NMOS transistor M4, thereby turning off transistor M4.
When NMOS transistor M3 turns on, NMOS transistor M3 immediately saturates, sinking a peak current given by Equation 1:IDS3=min [(KW3/L3)(VDD1−VTH)2; (KW5/L5)(VDD2−VTH)2+IEQ],  EQ.1where K=μC/2D, W3 is the width of transistor M3, L3 is the length of transistor M3, W5 is the width of transistor M5, L5 is the length of transistor M5, IEQ is the equivalent current of recharging all the parasitic capacitance associated with node OUTbar, and VTH is the threshold voltage. (IDS3=min[I3; I5] means the minimum of I3 and I5.)
At this point, NMOS transistor M3 sinks all of the current sourced by PMOS transistor M5 and a current from the inverted output node OUTbar, thereby pulling down the voltage on the inverted output node OUTbar. As the voltage on the inverted output node OUTbar falls, PMOS transistor M6 turns on when the gate-to-source voltage of transistor M6 falls below the threshold voltage of transistor M6.
Ideally, NMOS transistor M2 pulls down the voltage on the gate of NMOS transistor M4 and turns off transistor M4 before NMOS transistor M3 can pull down the voltage on the inverted output node OUTbar to turn on PMOS transistor M6. This minimizes the amount of shoot-through current (the current sourced by PMOS transistor M6 that is sunk by NMOS transistor M4).
When NMOS transistor M4 is turned off and PMOS transistor M6 is turned on, PMOS transistor M6 begins charging up the voltage on the output node OUT. Thus, at this point, NMOS transistor M3 is pulling down the voltage on the inverted output node OUTbar while PMOS transistor M6 is pulling up the voltage on the output node OUT.
Under normal operating conditions, as the voltage on the output node OUT continues to rise, PMOS transistor M5 turns off when the gate-to-source voltage of PMOS transistor M5 reaches the threshold voltage of PMOS transistor M5. When PMOS transistor M5 turns off, NMOS transistor M3 pulls the remaining voltage on the inverted output node OUTbar down to ground as PMOS transistor M6 charges the voltage on the output node OUT up to the second supply voltage VDD2.
Thus, the logic state on the output node OUT of level shifter 100 is the same as the logic state on the input node IN. Further, the voltage level of the logic high state has been level shifted up from 1.2V to 3.6V. In addition, the logic low state is present on the inverse output node OUTbar.
The sizes of transistors M3 and M5 are defined to guarantee that NMOS transistor M3 sinks all of the current sourced by PMOS transistor M5 after PMOS transistor M5 saturates. When the KW5/L5 of PMOS transistor M5 is not small enough in comparison with the KW3/L3 of NMOS transistor M3, and the second supply voltage VDD2 is large enough in comparison with the first supply voltage VDD1, then NMOS transistor M3 can not overdrive the current of PMOS transistor M5 and the circuit will never flip the states of nodes OUTbar and OUT.
Thus, a limitation on KW5/L5 has to be applied from the upper side for a given VDD1/VDD2 range and KW3/L3, causing the gm5 of PMOS transistor M5 to be substantially lower than the gm3 of NMOS transistor M3 if the circuit is designed to be working at a second supply voltage VDD2 that is larger than the first supply voltage VDD1 condition.
To insure that this condition is met, the saturation current IDS3 can be set to be equal to the saturation current ISD5 at the minimum possible value of the first supply voltage VDD1 and the maximum possible value of the second supply voltage VDD2. In addition, to insure against a worst case condition, the gate voltage of PMOS transistor M5 can be assumed to be zero volts. As a result, ISD5=(KW5/L5)(VDD2−VTH)2.
Setting the saturation current IDS3 to be equal to the saturation current ISD5 provides:(KW3/L3)(VDD1−VTH)2=(KW5/L5)(VDD2−VTH)2.
Rearranging provides:W3L5/L3W5=(VDD2−VTH)2/(VDD1−VTH)2.
Thus, by utilizing the above ratios, NMOS transistor M3 is guaranteed to sink all of the current sourced by PMOS transistor M5 after transistor M5 saturates. In addition, since NMOS transistors M3 and M4 are substantially the same size, and since PMOS transistors M5 and M6 are substantially the same size, the same ratios used for transistors M3 and M5 are also used for transistors M4 and M6.
One of the problems of level shifter 100 is that when level shifter 100 is used with a first supply voltage VDD1 that is smaller than the second supply voltage VDD2, the W5/L5 of PMOS transistor M5 has to be enough smaller than the W3/L3 of NMOS transistor M3 to reduce the gm5 of PMOS transistor M5.
This can be done by increasing the length L5 of PMOS transistor M5. However, as the channel length L5 increases, the speed of operation decreases. As a result, there is a need for a level shifter that provides high-speed operation between power domains that have a large voltage difference.